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Structure de mise en forme 2 colonnes

WP3 ‘s results for M18

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.  A SEM cross-section of the device is shown in Fig. 20.  The architecture features very small base active width, due to the self-alignment of the external base to the collector region, and the self-alignment of the emitter to the base. 

 


Figure 20: SEM cross-section of novel device

 

Fast thermal treatments to remove implantation damage and to activate impurities are usually carried out by spike anneals with ramp rates from 100K/s to 300K/s. Recently, techniques, like flash anneal, were developed which achieve ramp rates up to 105K/s.
Here a comprehensive study of the capability of the flash anneal for SiGe HBT fabrication is presented. Before starting integration lots, model experiments on blanket wafers are completed to study the effects of flash annealing on HBT-typical doping profiles and to find an appropriate temperature range for transistor functionality (Fig.21).
Static and dynamic transistor characteristics demonstrate the potential of this technique for improving the high-speed performance. However, the question, whether one can take an extra advantage by this method compared to a standard spike anneal or not, has to be explored further. For this purpose device architectures and processes are needed that take into account the strongly decreased diffusion lengths, in particular of the extrinsic base doping, due to the reduced thermal budget.


Figure 21: SIMS measurements of B profiles annealed at different temperatures with a conventional spike anneal (gray lines) or flash anneal (blue and red line).